- ARM Cortex-M4F
- Maximum supported frequency: 160MHz
- Supports DSP, FPU, MPU and NVIC
- Supports JTAG and SWD debug interfaces
- Code Flash: 2048KB
- Data Flash: 128KB
- SRAM: 256KB
- Instruction Cache: 16KB
- Two DMA engines with a total of 32 channels for more efficient data transfer
- Built-in internal signal interconnect module
- SysTick and RTC timers
- Supports ISO 26262 ASIL-B level
- ECC on Flash and SRAM reads
- On-chip clock monitoring
- On-chip power overvoltage and undervoltage monitoring
- On-chip temperature monitoring
- 3 hardware CRCs for data integrity check
- Built-in independent clock WDOG
- HSM engine for encryption and decryption
- Supports AES128/256, RSA1024/2048/3072/4096, ECC256, SM2/3/4, SHA224/256, TRNG, secure key storage and unique ID
- Supports secure boot and AES-CMAC authentication
- Compliant with the EVITA Full HSM specification
- Supports external crystal oscillator input: 8MHz ~ 40MHz
- Built-in high-precision HIRC: 24MHz
- Built-in low-power LIRC: 131.072KHz
- Built-in PLL
- ADC: 2 x 12-bit @1Mbps SAR ADC, 26 channels in total, built-in 2.5V reference voltage
- Analog comparator: two fast comparators with built-in 8-bit DAC
- 2 x CAN, each supporting CAN 2.0 and CAN-FD
- 4 x UART/LIN, each supporting LIN2.2 and SAE J2602
- 4 x SPI, each with 4 chip select signals
- 4 x I2C
- 7 x 16-bit PWM, 38 channels in total, supporting dead-zone complementary output, input capture, center-aligned and edge-aligned symmetric PWM output modes, and quadrature decoding
- 4 x 32-bit TRGT (Flexible Trigger Timers): 4 channels per TRGT
- 4 x 16-bit GPT (General Purpose Timer)
- AEC-Q100 Grade 1 (TA: -40 to 125°C)
- Package: QFN56