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SQ82201QHQ

Production
High Performance APLL with Multiple Output
Datasheet
SQ82201QHQ High Performance APLL with Multiple Output Datasheet
Part number SQ82201QHQ
Description Clock Generator
Outputs 3 differential + 7 Single End
Output freq range (MHz) 25/33.33/100/125/156.25
Input freq (MHz) 25
Inputs 2
Output banks 5
Core voltage (V) 3.3
Phase jitter typ RMS(fs) 150
RJ value of 1UI Jitter /
Package QFN6x6-40
  • 7 Single-ended LVCMOS Outputs:

-   One Single-ended LVCMOS 33.33MHz CPU Clock

-   Six Single-ended LVCMOS Outputs from the Reference Clock 

  • 3 LVPECL Differential Output Pairs, 1 pair 156.25MHz, 2 pairs selectable 100MHz and 125MHz 
  • Selectable Input Source: External Crystal or external Single-ended Input Source
  • 25MHz Crystal Oscillator Reference
  • RMS Phase Jitter 0.127ps(Typical)@ 156.25MHz, Reference 25MHz Crystal (12kHz~20MHz)
  • Power Supply Noise Rejection PSRR: -90dBc
  • 3.3V Power Supply Voltage
  • Ambient Operating Temperature: -40°C to 85°C
  • Package: QFN6x6-40

The SQ82201 is an analog PLL for Ethernet and processor applications. The SQ82201 will provide <0.15ps RMS phase jitter performance @ 156.25MHz and synthesize output 100MHz, 125MHz, 156.25MHz and a 33.33MHz CPU clock from a single device. Six LVCMOS outputs also serve as additional buffering of the 25MHz crystal reference; 3 differential output support LVPECL format.

Evaluation Board

  • 幻灯片1

    Photo of evaluation board

  • 幻灯片2

    Photo of evaluation board

  • 幻灯片3

    Photo of evaluation board

  • 幻灯片4

    Photo of evaluation board

  • 幻灯片5

    Photo of evaluation board

  • 幻灯片6

    Photo of evaluation board

EVB_SQ82201QHQ

The EVB_SQ82201QHQ is intended for High Performance APLL with Multiple Output.

Technical Documentation

Title Date
Silergy_Catalog_Q3_2026 2026-11-04